bus arbitration

The complex programmable logic unit CPLD was applied in the design of the bus arbitration organization.

在总线仲裁机构设计中应用了复杂可编程逻辑器件CPLD, 固化了和总线仲裁有关的总线逻辑关系.

网络文摘精选

Realize the interface between PCI9054 and the PCI bus, including the bus arbitration, read and write of the registers, the configuration of the EEPROM, the DMA transfer, interrupt response and so on.

实现PCI9054与计算机PCI总线的接口，包括总线仲裁，寄存器读写操作，EEPROM的配置和下载，DMA传输，中断响应等功能。

互联网摘选

In addition, a new algorithm for local bus arbitration is put forward, which is helpful in theory for future development.

另外，提出了性能比较好的本地总线仲裁算法，为后续开发做了理论上的探索。

互联网摘选

The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, and so on.

整个DSP芯片包括测试电路和各种外围设备，如DMA、总线仲裁、定时器等等。

互联网摘选

As a field bus, CAN, there are many advantages, such as non-destructive bus arbitration, exactly error detecting and definition; remote transmission distance and high speed in CAN bus.

而CAN作为一种现场总线，具有非破坏性总线仲裁、严格的错误检测和界定、通讯距离远、通讯速率高等优点，可以很好的满足农业温室系统中检测的需要。

互联网摘选

Design of PCI Bus Arbitration Device Based on FPGA

基于FPGA的PCI总线仲裁器设计

互联网摘选

The user-defined cell structure and cell bus arbitration are put forward, which can sustain the cross connection and series connection.

论文提出了一种自定义的信元结构，信元总线仲裁方式，这种信元总线交换技术支持设备的级联和交叉连接。

互联网摘选

It also introduces in detail the design thought of realizing system bus arbitration and logical control by largescale FPGA chip.

详细介绍了利用大规模FPGA芯片实现系统总线仲裁和逻辑控制的设计思想；

互联网摘选

The basic principle of PCI bus arbitration and the characteristic of CPLD/ FPGA are described. The design of PCI arbiter based on circular priority algorithm is realized with Verilog HDL. The simulation result is given.

介绍了PCI仲裁的原理，在此基础上描述了基于CPLD/FPGA的一种具有循环优先级通用的PCI仲裁器设计方案，并采用Verilog硬件描述语言设计实现，给出了仿真结果。

互联网摘选

The PCB of hardware system is completed under the guidance of high-speed circuit design theory. A new multi-DSP parallel interconnected structure based on bus arbitration is presented, which has the features of simple structure, flexible data transfer and multiple DSPs in equal status.

并在高速电路设计理论指导下完成了系统硬件平台PCB设计。提出了基于总线仲裁的新型多DSP对等全互连结构，该方法结构简单，数据传输灵活，多个DSP地位平等，不分主从。

互联网摘选

Within FPGA bus arbitration and communication protocol are realized.

总线仲裁及通信协议由FPGA编程实现。

互联网摘选

PC and DSP exchange data using high speed static RAM and bus arbitration circuit and corresponding handshake signal is designed to ensure the correct reading and writing RAM.

PC与DSP的数据交换采用高速静态RAM，并设计总线仲裁电路及相应的握手信号，以保证PC与DSP双方对RAM的正确读写。

互联网摘选

The mechanism of local bus arbitration is different from CPU and interface chip in the GPIB-VXI controller module.

在GPIB－VX1控制S模块中，CPU和接口芯片的本地总线仲裁机制不同，文中分别对其加以讨论，提出了一种实现各仲裁线之间的转换、切实可行的实际电路。

互联网摘选

The scheduling policy of the bus arbitration unit was been analyzed and the I/ O function of RTOS was partly implemented in hardware.

本文在分析总线仲裁单元的时间片调度的基础上，将操作系统的I／O管理的功能部分采用硬件实现。

互联网摘选

The basic principle of PCI bus arbitration is described and a PCI arbiter is designed in the paper.

论述了PCI仲裁的基本原理，给出了一个PCI仲裁器设计。

互联网摘选

The bue CAN has the functions of in polysleeve way, non-destructive bus arbitration technigue, super-strong-error measurement and high communication rate etc. which have been widely used in the various low cost, high anti-interference multi-machine systems.

CAN总线以其多主方式、非破坏性总线仲裁技术、超强错误检测和高通信速率等功能在各种低成本、高抗干扰的多机系统中得到了广泛应用。

互联网摘选

And the architecture of multiprocessors based on shared bus is an advisable architecture. The article has studied the bus arbitration mechanism of multiprocessor system architecture based on the characteristics of modern instrument. We selected the distributed arbiter and dynamic priority scheme to implement the target bus arbiter.

在分析现代仪器系统特点的基础上，研究了多微处理器系统的总线仲裁机制，选择了基于分布式仲裁方式和动态优先权策略作为系统的总线仲裁机制。

互联网摘选

Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.

实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；

互联网摘选

The design of bus arbitration module based on dynamic& static mixture algorithm

基于动静态混合算法的仲裁器模块设计

互联网摘选

Weighted Priority Rotational Algorithm on PCI Bus Arbitration

PCI总线加权优先循环仲裁算法

互联网摘选

The simple structure, flexible communication manner, special short frame format and effective bus arbitration technology make CAN bus a new way for highly reliable data transfer in industrial control and measurement system.

CAN总线以其简单的结构、灵活的通信方式、独特的短帧格式、高效的总线仲裁技术，为工业测控系统中高可靠性的数据传送提供了一种新的解决方案。

互联网摘选

It is a bus for multiple master computers with bus arbitration and high or low speed synchronization.

I2C总线是具备总线仲裁和高低速设备同步等功能的高性能多主机总线。

互联网摘选

The computer designed which was adopted the technology of bus arbitration and trouble isolation had the abilities such as the image processing.

所设计的星载计算机采用了总线仲裁和故障隔离技术，并具有图像处理等复杂功能。

互联网摘选

Performance and bus arbitration for DMA can be found in "DAB, DCB, and DEBPerformance" on another page.

DMA的性能及总线仲裁在其他页面的“DAB，DCB和DEB性能”中可以找到。

互联网摘选

On ATM side, both polling and priority control are used to perform cell bus arbitration. So the QoS control is provided and the cell transfer efficiency is enhanced.

ATM侧利用轮询和优先级控制共用来实现信元总线仲裁，从而实现业务服务质量控制，并提高信元传输效率。

互联网摘选

By topology optimization can make some of the nodes has a higher natural priority when bus arbitration.

另外通过对拓扑结构的优化使得某些节点在仲裁总线时具有更高的自然优先级。

互联网摘选

The structure of multiprocessor system is analyzed from the point of view of bus arbitration and LDF files.

分析多处理器系统的结构，从硬件方面的总线仲裁和软件方面的链接描述文件阐述多处理器系统调试的关键技术。

互联网摘选

Further investigation on the layered structure, frame form, error detection, node fault confinement, bus arbitration and bus synchronization of CAN is then launched.

然后对CAN总线的分层结构、帧格式、错误检测机制、节点故障界定机制、总线仲裁机制以及总线同步机制进行了深入研究。

互联网摘选